Sciweavers

301 search results - page 7 / 61
» Physical design techniques for optimizing RTA-induced variat...
Sort
View
PVLDB
2008
89views more  PVLDB 2008»
13 years 8 months ago
Constrained physical design tuning
Abstract Existing solutions to the automated physical design problem in database systems attempt to minimize execution costs of input workloads for a given storage constraint. In t...
Nicolas Bruno, Surajit Chaudhuri
DAC
2007
ACM
14 years 9 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
TWC
2008
114views more  TWC 2008»
13 years 8 months ago
Two dimensional cross-layer optimization for packet transmission over fading channel
In this paper a single-input-single-output wireless data transmission system with adaptive modulation and coding over correlated fading channel is considered, where run-time power ...
Xiaofeng Bai, Abdallah Shami
PACS
2004
Springer
146views Hardware» more  PACS 2004»
14 years 1 months ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 5 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen