This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with m polynomial in n, where each mesh node hosts a processor and a memory module. A...
Andrea Pietracaprina, Geppino Pucci, Jop F. Sibeyn
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
This paper presents Maya, a multi-paradigm, scalable and extensible network modeling framework for emulating distributed applications. A novel three-tier architecture is proposed ...
Junlan Zhou, Zhengrong Ji, Mineo Takai, Rajive Bag...
In this paper we propose the CTS (Concious Tutoring System) technology, a biologically plausible cognitive agent based on human brain functions.This agent is capable of learning a...
Usef Faghihi, Philippe Fournier-Viger, Roger Nkamb...