47 search results - page 6 / 10 » Pipelined hash-join on multithreaded architectures |
EUROPAR
2007
Springer
13 years 11 months ago
2007
Springer
Due to the increasing performance requirements of decoding H.264/AVC in HDTV or larger resolutions, new approaches are necessary to enable real-time processing. According to the cu...
APCSAC
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
ACMMSP
2005
ACM
14 years 28 days ago
2005
ACM
Combining ideas from several previous proposals, such as Active Pages, DIVA, and ULMT, we present the Memory Arithmetic Unit and Interface (MAUI) architecture. Because the “inte...
PDCAT
2004
Springer
14 years 22 days ago
2004
Springer
Abstract. This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...