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search results - page 195 / 195
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Planning with Reduced Operator Sets
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2011
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Computer Networks
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Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
12 years 8 months ago
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—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
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