Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Understanding why the performance of a multithreaded program does not improve linearly with the number of cores in a sharedmemory node populated with one or more multicore process...
In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able t...
Basilio B. Fraguela, Jose Renau, Paul Feautrier, D...
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
This paper describes the design, implementation and evaluation of Native Client, a sandbox for untrusted x86 native code. Native Client aims to give browser-based applications the...
Bennet Yee, David Sehr, Gregory Dardyk, J. Bradley...