37 search results - page 3 / 8 » Power Dissipation in Deep Submicron CMOS Digital Circuits |
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
ISLPED
2000
ACM
14 years 5 days ago
2000
ACM
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented cir...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...