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VLSID
1997
IEEE
106views VLSI» more  VLSID 1997»
15 years 10 months ago
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
S. Ramanathan, V. Visvanathan
IPPS
2007
IEEE
16 years 18 hour ago
RAxML-Cell: Parallel Phylogenetic Tree Inference on the Cell Broadband Engine
Computational phylogeny is a challenging application even for the most powerful supercomputers. It is also an ideal candidate for benchmarking emerging multiprocessor architecture...
Filip Blagojevic, Alexandros Stamatakis, Christos ...
ICPP
2009
IEEE
16 years 11 days ago
Fine-grain Parallelism Using Multi-core, Cell/BE, and GPU Systems: Accelerating the Phylogenetic Likelihood Function
We are currently faced with the situation where applications have increasing computational demands and there is a wide selection of parallel processor systems. In this paper we fo...
Frederico Pratas, Pedro Trancoso, Alexandros Stama...
176
Voted
CC
2008
Springer
144views System Software» more  CC 2008»
15 years 7 months ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
172
Voted
ASPLOS
2008
ACM
15 years 7 months ago
Tapping into the fountain of CPUs: on operating system support for programmable devices
The constant race for faster and more powerful CPUs is drawing to a close. No longer is it feasible to significantly increase the speed of the CPU without paying a crushing penalt...
Yaron Weinsberg, Danny Dolev, Tal Anker, Muli Ben-...