997 search results - page 6 / 200 » Power and Area Optimization for Multiple Restricted Multipli... |
ISMVL
2005
IEEE
14 years 28 days ago
2005
IEEE
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
ASAP
2008
IEEE
13 years 9 months ago
2008
IEEE
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
ICCV
2009
IEEE
15 years 9 days ago
2009
IEEE
Our objective is to obtain a state-of-the art object category
detector by employing a state-of-the-art image classifier
to search for the object in all possible image subwindows....
DAC
2007
ACM
14 years 8 months ago
2007
ACM
In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its effectiveness for digital FIR f...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...