1850 search results - page 279 / 370 » Power and performance optimization at the system level |
174
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BMCBI
2010
15 years 4 months ago
2010
Background: Computational comparison of two protein structures is the starting point of many methods that build on existing knowledge, such as structure modeling (including modeli...
151
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ISPDC
2010
IEEE
15 years 2 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
149
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GLVLSI
2000
IEEE
15 years 9 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
139
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TPDS
2008
15 years 4 months ago
2008
Multicore processors are an architectural paradigm shift that promises a dramatic increase in performance. But, they also bring an unprecedented level of complexity in algorithmic ...
147
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CODES
2008
IEEE
15 years 11 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...