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» Power minimization using control generated clocks
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ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
TOG
2008
102views more  TOG 2008»
13 years 8 months ago
Real-time data driven deformation using kernel canonical correlation analysis
Achieving intuitive control of animated surface deformation while observing a specific style is an important but challenging task in computer graphics. Solutions to this task can ...
Wei-Wen Feng, Byung-Uck Kim, Yizhou Yu
ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
14 years 2 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
HICSS
2007
IEEE
112views Biometrics» more  HICSS 2007»
14 years 3 months ago
The Next Generation of Monitoring and Control Systems Using Synchronized Sampling Technology and Multifunctional IEDs
This paper discusses implementation of the next generation solution for power system control and monitoring. The new design is based on the use of synchronized sampling technology...
Mladen Kezunovic
SIGMETRICS
2010
ACM
162views Hardware» more  SIGMETRICS 2010»
14 years 1 months ago
Coordinated power management of voltage islands in CMPs
Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based o...
Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kan...