732 search results - page 7 / 147 » Power minimization using control generated clocks |
DAC
2008
ACM
14 years 10 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
ISCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...
PDP
1997
IEEE
14 years 1 months ago
1997
IEEE
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
TVLSI
2002
13 years 8 months ago
2002
: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low...