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CODES
2006
IEEE
14 years 2 months ago
Floorplan driven leakage power aware IP-based SoC design space exploration
Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
LCPC
2004
Springer
14 years 1 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...
SAMOS
2010
Springer
13 years 6 months ago
Power aware heterogeneous MPSoC with dynamic task scheduling and increased data locality for multiple applications
A new heterogeneous multiprocessor system with dynamic memory and power management for improved performance and power consumption is presented. Increased data locality is automatic...
Oliver Arnold, Gerhard Fettweis
IPPS
2007
IEEE
14 years 2 months ago
Power-Aware Routing for Well-Nested Communications On The Circuit Switched Tree
Although algorithms that employ dynamic reconfiguration are extremely fast, they need the underlying architecture to change structure very rapidly, possibly at each step of the c...
Hatem M. El-Boghdadi
HIPC
2003
Springer
14 years 1 months ago
Power-Aware Adaptive Issue Queue and Register File
In this paper, we present a novel technique to reduce dynamic and static power dissipation in the issue queue. The proposed scheme is based on delaying the dispatch of instructions...
Jaume Abella, Antonio González