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DSD
2007
IEEE
132views Hardware» more  DSD 2007»
13 years 11 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge
SIGMOD
2000
ACM
99views Database» more  SIGMOD 2000»
13 years 12 months ago
WSQ/DSQ: A Practical Approach for Combined Querying of Databases and the Web
We present WSQ/DSQ (pronounced “wisk-disk”), a new approach for combining the query facilities of traditional databases with existing search engines on the Web. WSQ, for Web-S...
Roy Goldman, Jennifer Widom
WCRE
2002
IEEE
14 years 12 days ago
Estimating Potential Parallelism for Platform Retargeting
Scientific, symbolic, and multimedia applications present diverse computing workloads with different types of inherent parallelism. Tomorrow’s processors will employ varying com...
Linda M. Wills, Tarek M. Taha, Lewis B. Baumstark ...
LCPC
2004
Springer
14 years 26 days ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
13 years 11 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun