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» Predictable Instruction Caching for Media Processors
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ICS
2003
Tsinghua U.
14 years 17 days ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
WORDS
2002
IEEE
14 years 7 days ago
Writing Temporally Predictable Code
The Worst-Case Execution-Time Analysis (WCET Analysis) of program code that is to be executed on modern processors is a highly complex task. First, it involves path analysis, to i...
Peter P. Puschner, Alan Burns
JSA
2000
175views more  JSA 2000»
13 years 7 months ago
Complete worst-case execution time analysis of straight-line hard real-time programs
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. The analysis is focused on straight-line code...
Friedhelm Stappert, Peter Altenbernd
JPDC
2007
60views more  JPDC 2007»
13 years 7 months ago
The impact of wrong-path memory references in cache-coherent multiprocessor systems
The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
CODES
2009
IEEE
13 years 11 months ago
TotalProf: a fast and accurate retargetable source code profiler
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers...