86 search results - page 9 / 18 » Predictable Instruction Caching for Media Processors |
ISPASS
2010
IEEE
14 years 3 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
MICRO
1998
IEEE
14 years 20 days ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
ISCA
1995
IEEE
13 years 12 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
ICS
2004
Tsinghua U.
14 years 1 months ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
PLDI
2005
ACM
14 years 2 months ago
2005
ACM
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...