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» Predictable performance in SMT processors
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SIGMETRICS
2005
ACM
156views Hardware» more  SIGMETRICS 2005»
14 years 2 months ago
Evaluating the impact of simultaneous multithreading on network servers using real hardware
This paper examines the performance of simultaneous multithreading (SMT) for network servers using actual hardware, multiple network server applications, and several workloads. Us...
Yaoping Ruan, Vivek S. Pai, Erich M. Nahum, John M...
ACL
2010
13 years 7 months ago
A Joint Rule Selection Model for Hierarchical Phrase-Based Translation
In hierarchical phrase-based SMT systems, statistical models are integrated to guide the hierarchical rule selection for better translation performance. Previous work mainly focus...
Lei Cui, Dongdong Zhang, Mu Li, Ming Zhou, Tiejun ...
ICS
2000
Tsinghua U.
14 years 15 days ago
Characterizing processor architectures for programmable network interfaces
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...
PDCAT
2004
Springer
14 years 2 months ago
An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications
Abstract. This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces...
Byung In Moon, Hongil Yoon, Ilgun Yun, Sungho Kang
WMPI
2004
ACM
14 years 2 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar