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» Predictable performance in SMT processors
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CASES
2006
ACM
14 years 2 months ago
Automatic performance model construction for the fast software exploration of new hardware designs
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
John Cavazos, Christophe Dubach, Felix V. Agakov, ...
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 3 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
PDPTA
2003
13 years 10 months ago
An Interactive Tuning Support for Processor Allocation of Data-Driven Realtime Programs
This paper presents the effectiveness of an interactive support facility to tune processor allocation of data-driven realtime programs on CUE (Coordinating Users’ requirements an...
Yasuhiro Wabiko, Hiroaki Nishikawa
CASES
2008
ACM
13 years 10 months ago
Exploring and predicting the architecture/optimising compiler co-design space
Embedded processor performance is dependent on both the underlying architecture and the compiler optimisations applied. However, designing both simultaneously is extremely difficu...
Christophe Dubach, Timothy M. Jones, Michael F. P....
IPPS
2009
IEEE
14 years 3 months ago
Revisiting communication performance models for computational clusters
—In this paper, we analyze restrictions of traditional models affecting the accuracy of analytical prediction of the execution time of collective communication operations. In par...
Alexey L. Lastovetsky, Vladimir Rychkov, Maureen O...