492 search results - page 79 / 99 » Predictable performance in SMT processors |
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
14 years 2 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
SBACPAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
RTAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
JPDC
2006
13 years 7 months ago
2006
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
ICS
2009
Tsinghua U.
14 years 4 days ago
2009
Tsinghua U.
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...