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» Predictable performance in SMT processors
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GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
13 years 6 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
14 years 3 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...
SAMOS
2007
Springer
14 years 3 months ago
On the Problem of Minimizing Workload Execution Time in SMT Processors
Abstract—Most research work on (Simultaneous Multithreading Processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a wor...
Francisco J. Cazorla, Enrique Fernández, Pe...
EUROPAR
2004
Springer
14 years 2 months ago
Feasibility of QoS for SMT
Since embedded systems require ever more compute power, SMT processors are viable candidates for future high performance embedded processors. However, SMTs exhibit unpredictable pe...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
HIPEAC
2007
Springer
14 years 3 months ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...