Sciweavers

180 search results - page 9 / 36
» Prediction error of a fault tolerant neural network
Sort
View
ICONIP
2007
13 years 10 months ago
Analysis on Bidirectional Associative Memories with Multiplicative Weight Noise
Abstract. In neural networks, network faults can be exhibited in different forms, such as node fault and weight fault. One kind of weight faults is due to the hardware or software ...
Chi-Sing Leung, Pui-Fai Sum, Tien-Tsin Wong
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
14 years 2 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
ICT
2004
Springer
194views Communications» more  ICT 2004»
14 years 2 months ago
Competitive Neural Networks for Fault Detection and Diagnosis in 3G Cellular Systems
We propose a new approach to fault detection and diagnosis in third-generation (3G) cellular networks using competitive neural algorithms. For density estimation purposes, a given ...
Guilherme De A. Barreto, João Cesar M. Mota...
DSN
2005
IEEE
14 years 2 months ago
How Resilient are Distributed f Fault/Intrusion-Tolerant Systems?
Fault-tolerant protocols, asynchronous and synchronous alike, make stationary fault assumptions: only a fraction f of the total n nodes may fail. Whilst a synchronous protocol is ...
Paulo Sousa, Nuno Ferreira Neves, Paulo Verí...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 2 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...