47 search results - page 8 / 10 » Prefetch-Aware DRAM Controllers |
HPDC
1999
IEEE
14 years 2 months ago
1999
IEEE
Efficient and robust metacomputing requires the decomposition of complex jobs into tasks that must be scheduled on distributed processing nodes. There are various ways of creating...
SIGOPSE
2004
ACM
14 years 3 months ago
2004
ACM
This position paper argues that policies for physical memory management and for memory power mode control should be relocated to the system software of a programmable memory manag...
ISCA
2012
IEEE
12 years 7 days ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
HPCA
1999
IEEE
14 years 2 months ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
ISW
2009
Springer
14 years 4 months ago
2009
Springer
We present ShMAC (Shallow MAC), a fixed input length message authentication code that performs most of the computation prior to the availability of the message. Specifically, Sh...