This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
Delays in the check-in system at an airport vary with times of the day, day of the week, and types of check-in modes chosen by the passengers. Extensive data collection of the che...
Simone Appelt, Rajan Batta, Li Lin, Colin G. Drury
Planning for manufacturing workpiecesis a complex task that requires the interaction of a domain-specific reasoner and a generic planning mechanism.In this paper wepresent an arch...
A model of unrestricted And-parallel execution for logic programs is described, based on Dependency Directed Backtracking (DDBT) aimed at improving the efficiency of execution whi...
—The research efforts of the DECIDE Research Group have resulted in a decision tool capable of handling imprecise information in complex decision situations. Some of the research...