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ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
14 years 1 months ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
GLVLSI
2009
IEEE
146views VLSI» more  GLVLSI 2009»
13 years 11 months ago
A reconfigurable stochastic architecture for highly reliable computing
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan...
FPL
2008
Springer
86views Hardware» more  FPL 2008»
13 years 9 months ago
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Ha...
ERSA
2007
194views Hardware» more  ERSA 2007»
13 years 9 months ago
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
Ross Brennan, Michael Manzke, Keith O'Conor, John ...
FPL
2009
Springer
106views Hardware» more  FPL 2009»
14 years 9 days ago
Coarse-grained dynamically reconfigurable architecture with flexible reliability
This paper proposes a coarse-grained dynamically reconfigurable architecture, which offers flexible reliability to soft errors and aging. A notion of cluster is introduced as a ...
Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hir...