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FPL
1995
Springer
137views Hardware» more  FPL 1995»
13 years 11 months ago
High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform
General purpose custom computing platforms, such as Splash-2, have demonstrated the ability to enter mainstream computing not only due to their near application-specific speeds bu...
Ramana V. Rachakonda, Peter M. Athanas, A. Lynn Ab...
ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
13 years 12 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
14 years 1 months ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...
ISCAS
2002
IEEE
89views Hardware» more  ISCAS 2002»
14 years 17 days ago
ESD protection circuits with novel MOS-bounded diode structures
On-chip ESD protection circuits realized with novel diode structures without the field-oxide boundary across the p/n junction are proposed. A PMOS (NMOS) is especially inserted in...
Ming-Dou Ker, Che-Hao Chuang
ASPDAC
2007
ACM
132views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach
- This paper proposes a fast and practical decoupling capacitor (decap) budgeting algorithm to optimize the power ground (P/G) network design. The new method adopts a modified rand...
Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong,...