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» Processor Architectures for Ontogenesis
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ICC
2007
IEEE
127views Communications» more  ICC 2007»
15 years 11 months ago
A Memory Unit for Priority Management in IPSec Accelerators
— This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at d...
Luigi Dadda, Alberto Ferrante, Marco Macchetti
132
Voted
ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
16 years 1 months ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...
CASES
2006
ACM
15 years 8 months ago
High-performance packet classification algorithm for many-core and multithreaded network processor
Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based cla...
Duo Liu, Bei Hua, Xianghui Hu, Xinan Tang
146
Voted
ASAP
2006
IEEE
97views Hardware» more  ASAP 2006»
15 years 10 months ago
Dynamic-SIMD for lens distortion compensation
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Ba...
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
15 years 10 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu