378 search results - page 50 / 76 » Processor Modeling for Hardware Software Codesign |
VTS
2002
IEEE
13 years 11 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
PPOPP
2010
ACM
14 years 1 months ago
2010
ACM
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
CASES
2006
ACM
13 years 10 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
DSN
2005
IEEE
14 years 12 days ago
2005
IEEE
Hardware dependability improvements have led to a situation in which it is sometimes unnecessary to employ extensive hardware replication to mask hardware faults. Expanding upon o...