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ISCA
1996
IEEE
120views Hardware» more  ISCA 1996»
14 years 2 months ago
Missing the Memory Wall: The Case for Processor/Memory Integration
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
14 years 22 days ago
System-level design space exploration for security processor prototyping in analytical approaches
— The customization of architectures in designing the security processor-based systems typically involves timeconsuming simulation and sophisticated analysis in the exploration o...
Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee
FPL
2008
Springer
129views Hardware» more  FPL 2008»
14 years 9 days ago
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...
PDPTA
2003
14 years 3 days ago
DSMSim: A Distributed Shared Memory Simulator for Clusters of Symmetric Multi-Processors
Distributed shared memory systems have become popular as a means of utilizing clusters of computers for solving large applications. We have developed a high-performance DSM at Way...
Darshan Thaker, Vipin Chaudhary
HPCA
2009
IEEE
14 years 11 months ago
Blueshift: Designing processors for timing speculation from the ground up
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey ...