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ISCA
1992
IEEE
151views Hardware» more  ISCA 1992»
14 years 2 months ago
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yos...
IJES
2008
102views more  IJES 2008»
13 years 10 months ago
Alternative application-specific processor architectures for fast arbitrary bit permutations
Block ciphers are used to encrypt data and provide data confidentiality. For interoperability reasons, it is desirable to support a variety of block ciphers efficiently. Of the bas...
Zhijie Jerry Shi, Xiao Yang, Ruby B. Lee
TACAS
2010
Springer
210views Algorithms» more  TACAS 2010»
14 years 5 months ago
Automatic Analysis of Scratch-Pad Memory Code for Heterogeneous Multicore Processors
Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small “scratchpad” memories. The price for increase...
Alastair F. Donaldson, Daniel Kroening, Philipp R&...
DSD
2008
IEEE
145views Hardware» more  DSD 2008»
14 years 5 months ago
Formulating MITF for a Multicore Processor with SEU Tolerance
While shrinking geometries of embedded LSI devices is beneficial for portable intelligent systems, it is increasingly susceptible to influences from electrical noise, process vari...
Toshimasa Funaki, Toshinori Sato
IPPS
2007
IEEE
14 years 5 months ago
SWARM: A Parallel Programming Framework for Multicore Processors
Due to fundamental physical limitations and power constraints, we are witnessing a radical change in commodity microprocessor architectures to multicore designs. Continued perform...
David A. Bader, Varun Kanade, Kamesh Madduri