Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
This work implements and analyses a highway traffic flow simulation based on continuum modeling of traffic dynamics. A traffic-flow simulation was developed and mapped onto a para...
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to varied system configurations (e.g., number of processors) and workload behaviors...
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, ...
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
We present a model for the parallel performance of algorithms that consist of concurrent, two-dimensional wavefronts implemented in a message passing environment. The model combine...
Adolfy Hoisie, Olaf M. Lubeck, Harvey J. Wasserman