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» Program algebra with unit instruction operators
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RTSS
2006
IEEE
14 years 1 months ago
MCGREP - A Predictable Architecture for Embedded Real-Time Systems
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
Jack Whitham, Neil C. Audsley
MICRO
1994
IEEE
81views Hardware» more  MICRO 1994»
13 years 11 months ago
Register file port requirements of transport triggered architectures
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
Jan Hoogerbrugge, Henk Corporaal
CASES
2008
ACM
13 years 9 months ago
Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...
Hoseok Chang, Wonyong Sung
LCTRTS
2007
Springer
14 years 1 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
HPCA
1999
IEEE
13 years 11 months ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi