30 search results - page 5 / 6 » Program algebra with unit instruction operators |
ESTIMEDIA
2005
Springer
14 years 10 days ago
2005
Springer
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
ASPDAC
2001
ACM
13 years 10 months ago
2001
ACM
Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and...
ICFP
2012
ACM
11 years 9 months ago
2012
ACM
Graphics processing units (GPUs) provide both memory bandwidth and arithmetic performance far greater than that available on CPUs but, because of their Single-Instruction-Multiple...
ARVLSI
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
IISWC
2009
IEEE
14 years 1 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...