Sciweavers

852 search results - page 116 / 171
» Programmable Packet Scheduling
Sort
View
240
Voted
HPDC
2012
IEEE
13 years 4 months ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...
138
Voted
PPOPP
2010
ACM
15 years 11 months ago
GAMBIT: effective unit testing for concurrency libraries
As concurrent programming becomes prevalent, software providers are investing in concurrency libraries to improve programmer productivity. Concurrency libraries improve productivi...
Katherine E. Coons, Sebastian Burckhardt, Madanlal...
OSDI
2004
ACM
16 years 2 months ago
MapReduce: Simplified Data Processing on Large Clusters
MapReduce is a programming model and an associated implementation for processing and generating large data sets. Users specify a map function that processes a key/value pair to ge...
Jeffrey Dean, Sanjay Ghemawat
107
Voted
SIGCOMM
2009
ACM
15 years 9 months ago
DECOR: DEClaritive network management and OpeRation
Network management operations are complicated, tedious and error-prone, requiring significant human involvement and expert knowledge. In this paper, we first examine the fundame...
Xu Chen, Yun Mao, Zhuoqing Morley Mao, Jacobus E. ...
RTAS
2007
IEEE
15 years 8 months ago
Optimizing the FPGA Implementation of HRT Systems
The availability of programmable hardware devices with high density of logic elements and the possibility of implementing CPUs (called softcores) using a fraction of the FPGA area...
Marco Di Natale, Enrico Bini