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DELTA
2008
IEEE
14 years 4 months ago
A Visual Notation for Processor and Resource Scheduling
Scheduling of concurrent processors in a real-time image processing system on FPGA (Field programmable gate array) hardware is a not a trivial task. We propose a number of graphic...
Christopher T. Johnston, Paul J. Lyons, Donald G. ...
CN
2004
138views more  CN 2004»
13 years 9 months ago
Performance evaluation of prioritized scheduling with buffer management for differentiated services architectures
Differentiated services (DiffServ) is an architecture for the Internet in which various applications are supported using a simple classification scheme. Packets entering the DiffS...
Ahmed E. Kamal, Hossam S. Hassanein
FCCM
2003
IEEE
185views VLSI» more  FCCM 2003»
14 years 3 months ago
Implementation of a Content-Scanning Module for an Internet Firewall
A module has been implemented in Field Programmable Gate Array (FPGA) hardware that scans the content of Internet packets at Gigabit/second rates. All of the packet processing ope...
James Moscola, John W. Lockwood, Ronald Prescott L...
CN
2006
109views more  CN 2006»
13 years 10 months ago
Quality of service provisioning for composable routing elements
Quality of service (QoS) provisioning for dynamically composable software elements in a programmable router has not received much attention. We present a router platform that supp...
Seung Chul Han, Puneet Zaroo, David K. Y. Yau, Yu ...
FOCS
2003
IEEE
14 years 3 months ago
Switch Scheduling via Randomized Edge Coloring
The essence of an Internet router is an n ¡ n switch which routes packets from input to output ports. Such a switch can be viewed as a bipartite graph with the input and output p...
Gagan Aggarwal, Rajeev Motwani, Devavrat Shah, An ...