304 search results - page 42 / 61 » Programmable memory blocks supporting content-addressable me... |
PPOPP
2012
ACM
12 years 3 months ago
2012
ACM
This paper introduces a programming interface called PARRAY (or Parallelizing ARRAYs) that supports system-level succinct programming for heterogeneous parallel systems like GPU c...
SPAA
2004
ACM
14 years 1 months ago
2004
ACM
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
DSL
1997
13 years 9 months ago
1997
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
PC
2010
13 years 6 months ago
2010
We consider the computation of shortest paths on Graphic Processing Units (GPUs). The blocked recursive elimination strategy we use is applicable to a class of algorithms (such as...
ICDE
2007
IEEE
14 years 9 months ago
2007
IEEE
It has long been recognized that multi-stream operators, such as union and join, often have to wait idly in a temporarily blocked state, as a result of skews between the timestamp...