304 search results - page 42 / 61 » Programmable memory blocks supporting content-addressable me... |
171
Voted
PPOPP
2012
ACM
13 years 10 months ago
2012
ACM
This paper introduces a programming interface called PARRAY (or Parallelizing ARRAYs) that supports system-level succinct programming for heterogeneous parallel systems like GPU c...
132
Voted
SPAA
2004
ACM
15 years 8 months ago
2004
ACM
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
126
Voted
DSL
1997
15 years 3 months ago
1997
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
134
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PC
2010
15 years 29 days ago
2010
We consider the computation of shortest paths on Graphic Processing Units (GPUs). The blocked recursive elimination strategy we use is applicable to a class of algorithms (such as...
221
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ICDE
2007
IEEE
16 years 3 months ago
2007
IEEE
It has long been recognized that multi-stream operators, such as union and join, often have to wait idly in a temporarily blocked state, as a result of skews between the timestamp...