304 search results - page 43 / 61 » Programmable memory blocks supporting content-addressable me... |
SIPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for ...
LCN
2005
IEEE
14 years 1 months ago
2005
IEEE
A combined input and crosspoint queued (CICQ) switch with a flow control latency of round-trip time (RTT) packets requires each crosspoint (CP) buffer to hold the RTT packets in o...
CHES
2005
Springer
14 years 1 months ago
2005
Springer
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
Abstract—Cyber-Physical Systems require distributed architectures to support safety critical real-time control. Kopetz’ Time-Triggered Architectures (TTA) have been proposed as...