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» Programming the FlexRAM parallel intelligent memory system
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OOPSLA
2010
Springer
15 years 28 days ago
Cross-language, type-safe, and transparent object sharing for co-located managed runtimes
As software becomes increasingly complex and difficult to analyze, it is more and more common for developers to use high-level, type-safe, object-oriented (OO) programming langua...
Michal Wegiel, Chandra Krintz
133
Voted
ASPLOS
1998
ACM
15 years 6 months ago
Data Speculation Support for a Chip Multiprocessor
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
Lance Hammond, Mark Willey, Kunle Olukotun
175
Voted
OOPSLA
2010
Springer
15 years 28 days ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
136
Voted
IPPS
2006
IEEE
15 years 8 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
PADS
1996
ACM
15 years 6 months ago
Design of High Level Modelling / High Performance Simulation Environments
Advances in massively parallel platforms are increasing the prospects for high performance discrete event simulation. Still the di culty in parallel programming persists and there...
Bernard P. Zeigler, Doohwan Kim