The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are ch...
Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyu...
This paper describes the participation of RICOH in the monolingual and cross-lingual information retrieval tasks on German Indexing and Retrieval Testdatabase (GIRT) in the Cross-L...
The paper deals with the process of designing a phonetically and prosodically rich speech corpus for unit selection speech synthesis. The attention is given mainly to the recordin...
In PLT Scheme, programs consist of modules with contracts. The latter describe the inputs and outputs of functions and objects via predicates. A run-time system enforces these pre...
Philippe Meunier, Robert Bruce Findler, Matthias F...
This paper proposes a Highly-Available Open Shortest Path First (HA-OSPF) router which consists of two OSPF router modules-active and standby-to support a highavailability network...