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IPPS
2006
IEEE
14 years 1 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
IEEEPACT
2008
IEEE
14 years 1 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
PLDI
2006
ACM
14 years 1 months ago
Optimizing memory transactions
Atomic blocks allow programmers to delimit sections of code as ‘atomic’, leaving the language’s implementation to enforce atomicity. Existing work has shown how to implement...
Timothy L. Harris, Mark Plesko, Avraham Shinnar, D...
IPCCC
2007
IEEE
14 years 1 months ago
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
Lu Peng, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-K...
CGO
2006
IEEE
13 years 11 months ago
Profiling over Adaptive Ranges
Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. This p...
Shashidhar Mysore, Banit Agrawal, Timothy Sherwood...