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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 2 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
DAC
1999
ACM
14 years 1 months ago
Robust Techniques for Watermarking Sequential Circuit Designs
We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on th...
Arlindo L. Oliveira
ICCTA
2007
IEEE
14 years 1 months ago
What Graphs can be Efficiently Represented by BDDs?
We have carried out experimental research into implicit representation of large graphs using reduced ordered binary decision diagrams (OBDDs). We experimentally show that for grap...
Changxing Dong, Paul Molitor
RANDOM
1998
Springer
14 years 1 months ago
Using Approximation Hardness to Achieve Dependable Computation
Abstract. Redundancy has been utilized to achieve fault tolerant computation and to achieve reliable communication in networks of processors. These techniques can only be extended ...
Mike Burmester, Yvo Desmedt, Yongge Wang
CORR
2006
Springer
95views Education» more  CORR 2006»
13 years 9 months ago
Naming Games in Spatially-Embedded Random Networks
We investigate a prototypical agent-based model, the Naming Game, on random geometric networks. The Naming Game is a minimal model, employing local communications that captures th...
Qiming Lu, Gyorgy Korniss, Boleslaw K. Szymanski