544 search results - page 20 / 109 » Reading to Write |
ICS
2003
Tsinghua U.
14 years 1 months ago
2003
Tsinghua U.
In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these pararmeters g...
HPCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
ICPP
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we present a hierarchical Data Cache Architecture called DCA to effectively slash local interconnect traffic and thus boost the storage server performance. DCA is ...
PODC
2005
ACM
14 years 2 months ago
2005
ACM
The obstruction-free Dynamic Software Transactional Memory (DSTM) system of Herlihy et al. allows only one transaction at a time to acquire an object for writing. Should a second ...
SPAA
2006
ACM
14 years 2 months ago
2006
ACM
This paper investigates time-efficient implementations of atomic read-write registers in message-passing systems where the number of readers can be unbounded. In particular we st...