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ICS
2003
Tsinghua U.
14 years 2 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
ICWE
2003
Springer
14 years 2 months ago
Semi-automatic Assessment Process in a Ubiquitous Environment for Language Learning
This work presents a research on the methods and mechanisms necessary to bring the Information and Communication Technologies in the traditional classroom. This will be achieved by...
Maximiliano Paredes, Manuel Ortega, Pedro P. S&aac...
PLDI
2010
ACM
14 years 2 months ago
Adversarial memory for detecting destructive races
Multithreaded programs are notoriously prone to race conditions, a problem exacerbated by the widespread adoption of multi-core processors with complex memory models and cache coh...
Cormac Flanagan, Stephen N. Freund
INFOCOM
2002
IEEE
14 years 2 months ago
Towards Simple, High-performance Schedulers for High-aggregate Bandwidth Switches
— High-aggregate bandwidth switches are those whose port count multiplied by the operating line rate is very high; for example, a 30 port switch operating at 40 Gbps or a 1000 po...
Paolo Giaccone, Balaji Prabhakar, Devavrat Shah
ISCA
2002
IEEE
93views Hardware» more  ISCA 2002»
14 years 2 months ago
Transient-Fault Recovery Using Simultaneous Multithreading
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
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