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CJ
2006
84views more  CJ 2006»
13 years 10 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
ICDE
2010
IEEE
227views Database» more  ICDE 2010»
14 years 5 months ago
Incorporating partitioning and parallel plans into the SCOPE optimizer
— Massive data analysis on large clusters presents new opportunities and challenges for query optimization. Data partitioning is crucial to performance in this environment. Howev...
Jingren Zhou, Per-Åke Larson, Ronnie Chaiken
ASP
2005
Springer
14 years 4 days ago
Exploiting ASP for Semantic Information Extraction
Abstract. The paper describes HıLεX, a new ASP-based system for the extraction of information from unstructured documents. Unlike previous systems, which are mainly syntactic, H...
Massimo Ruffolo, Nicola Leone, Marco Manna, Domeni...
LPAR
2001
Springer
14 years 2 months ago
Local Conditional High-Level Robot Programs
When it comes to building robot controllers, highlevel programming arises as a feasible alternative to planning. The task then is to verify a high-level program by finding a lega...
Sebastian Sardiña
JSA
2007
191views more  JSA 2007»
13 years 10 months ago
Automated memory-aware application distribution for Multi-processor System-on-Chips
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
Heikki Orsila, Tero Kangas, Erno Salminen, Timo D....