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ICS
2003
Tsinghua U.
14 years 22 days ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
PLDI
2010
ACM
14 years 18 days ago
Adversarial memory for detecting destructive races
Multithreaded programs are notoriously prone to race conditions, a problem exacerbated by the widespread adoption of multi-core processors with complex memory models and cache coh...
Cormac Flanagan, Stephen N. Freund
ISCA
2002
IEEE
93views Hardware» more  ISCA 2002»
14 years 14 days ago
Transient-Fault Recovery Using Simultaneous Multithreading
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
SAC
2009
ACM
14 years 6 days ago
Impact of function inlining on resource-constrained embedded systems
With the development of computer systems, function inlining schemes were used to reduce execution time while increasing codes. In embedded systems such as wireless sensor nodes, t...
Bongjae Kim, Sangho Yi, Yookun Cho, Jiman Hong
IPPS
1999
IEEE
13 years 11 months ago
Improving Collective I/O Performance Using Threads
Massively parallel computers are increasingly being used to solve large, I/O intensive applications in many different fields. For such applications, the I/O requirements quite oft...
Phillip M. Dickens, Rajeev Thakur