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129
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ICS
2003
Tsinghua U.
15 years 8 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
137
Voted
SOUPS
2009
ACM
15 years 9 months ago
Graphical passwords as browser extension: implementation and usability study
Abstract: Today, most Internet applications still establish user authentication with traditional text based passwords. Designing a secure as well as a user-friendly password-based ...
Kemal Bicakci, Mustafa Yuceel, Burak Erdeniz, Haka...
EUROSYS
2007
ACM
15 years 12 months ago
Sprint: a middleware for high-performance transaction processing
Sprint is a middleware infrastructure for high performance and high availability data management. It extends the functionality of a standalone in-memory database (IMDB) server to ...
Lásaro J. Camargos, Fernando Pedone, Marcin...
117
Voted
OOPSLA
2004
Springer
15 years 8 months ago
Hard real-time: C++ versus RTSJ
In the domain of hard real-time systems, which language is better: C++ or the Real-Time Specification for Java (RTSJ)? Although standard Java provides a more productive programmin...
Daniel L. Dvorak, William K. Reinholtz
175
Voted
HPDC
2012
IEEE
13 years 5 months ago
Dynamic adaptive virtual core mapping to improve power, energy, and performance in multi-socket multicores
Consider a multithreaded parallel application running inside a multicore virtual machine context that is itself hosted on a multi-socket multicore physical machine. How should the...
Chang Bae, Lei Xia, Peter A. Dinda, John R. Lange