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EUROPAR
2010
Springer
13 years 8 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...
ISPASS
2005
IEEE
14 years 1 months ago
Performance Characterization of Java Applications on SMT Processors
As Java is emerging as one of the major programming languages in software development, studying how Java applications behave on recent SMT processors is of great interest. This pa...
Wei Huang, Jiang Lin, Zhao Zhang, J. Morris Chang
IEEEINTERACT
2002
IEEE
14 years 11 days ago
On the Predictability of Program Behavior Using Different Input Data Sets
Smaller input data sets such as the test and the train input sets are commonly used in simulation to estimate the impact of architecture/micro-architecture features on the perform...
Wei-Chung Hsu, Howard Chen, Pen-Chung Yew, Dong-yu...
ICPADS
2005
IEEE
14 years 1 months ago
A Hybrid Web Server Architecture for e-Commerce Applications
The performance of an e-commerce application can be measured according to technical metrics but also following business indicators. The revenue obtained by a commercial web applic...
David Carrera, Vicenç Beltran, Jordi Torres...
IEEEPACT
2006
IEEE
14 years 1 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev