30 search results - page 5 / 6 » Reduced Delay BCD Adder |
ISCAS
1993
IEEE
13 years 11 months ago
1993
IEEE
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...