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» Reducing Compilation Time Overhead in Compiled Simulators
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FPL
1998
Springer
106views Hardware» more  FPL 1998»
14 years 6 days ago
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
Abstract. We present different architectures to solve Boolean satisfiability problems in instance-specific hardware. A simulation of these architectures shows that for examples fro...
Marco Platzner, Giovanni De Micheli
IEEEPACT
1999
IEEE
14 years 8 days ago
Predicated Static Single Assignment
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
IJPP
2000
94views more  IJPP 2000»
13 years 7 months ago
Path Analysis and Renaming for Predicated Instruction Scheduling
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
APLAS
2004
ACM
14 years 1 months ago
Network Fusion
Modular programming enjoys many well-known advantages: readability, maintainability, separate development and compilation. However, the composition of modular units (components) s...
Pascal Fradet, Stéphane Hong Tuan Ha
SE
2008
13 years 9 months ago
Eliminating Trust From Application Programs By Way Of Software Architecture
: In many of today's application programs, security functionality is inseparably intertwined with the actual mission-purpose logic. As a result, the trusted code base is unnec...
Michael Franz