155 search results - page 16 / 31 » Reducing Design Complexity of the Load Store Queue |
ICDCS
2008
IEEE
14 years 2 months ago
2008
IEEE
Declustering techniques reduce query response times through parallel I/O by distributing data among multiple devices. Recently, replication based approaches were proposed to furth...
DAC
2007
ACM
13 years 12 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
SPAA
2003
ACM
14 years 1 months ago
2003
ACM
The current literature offers two extremes of nonblocking software synchronization support for concurrent data structure design: intricate designs of specific structures based o...
CSREAESA
2003
13 years 9 months ago
2003
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
As computing breaches petascale limits both in processor performance and storage capacity, the only way that current and future gains in performance can be achieved is by increasi...