155 search results - page 5 / 31 » Reducing Design Complexity of the Load Store Queue |
JCM
2008
13 years 8 months ago
2008
In this paper we revisit the minimum mean square error (MMSE) pilot-aided channel estimation for broadband orthogonal frequency division multiplexing (OFDM) systems. The careful de...
ISCA
2002
IEEE
14 years 29 days ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
CC
2004
Springer
14 years 1 months ago
2004
Springer
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
JSA
2010
13 years 6 months ago
2010
— Effective address calculation for load and store instructions needs to compete for ALU with other instructions and hence extra latencies might be incurred to data cache accesse...