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ASPLOS
1996
ACM
13 years 11 months ago
Reducing Network Latency Using Subpages in a Global Memory Environment
New high-speed networks greatly encourage the use of network memory as a cache for virtual memory and file pages, thereby reducing the need for disk access. Becausepages are the f...
Hervé A. Jamrozik, Michael J. Feeley, Geoff...
IPPS
2000
IEEE
14 years 23 hour ago
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
Jim Nilsson, Fredrik Dahlgren
HPDC
1996
IEEE
13 years 11 months ago
Shared Memory NUMA Programming on I-WAY
The performance of the Global Array shared-memory nonuniform memory-access programming model is explored on the I-WAY, wide-area-network distributed supercomputer environment. The...
Jarek Nieplocha, Robert J. Harrison
DAC
2001
ACM
14 years 8 months ago
Route Packets, Not Wires: On-Chip Interconnection Networks
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
William J. Dally, Brian Towles
SC
1995
ACM
13 years 11 months ago
A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
Thomas L. Sterling, Daniel Savarese, Peter MacNeic...